1. Technical Field
The present disclosure relates to electrically erasable and programmable non-volatile memories (EEPROM). The present disclosure relates more particularly to a non-volatile memory, comprising memory cells each comprising a floating-gate transistor and a select transistor gate shared with a so-called “twin” adjacent memory cell.
2. Description of the Related Art
FIG. 1 is a wiring diagram of memory cells C11, C12 of the above-mentioned type, belonging to two adjacent pages Pi, Pi+1 of a memory array. The memory cells C11, C12 are read- and write-accessible through a bit line BL, a word line WL<i,i+1> and control gate lines CGL<i>, CGL<i+1>. Each memory cell comprises a floating-gate transistor, respectively FGT11, FGT12. A control gate CG of the transistor FGT11 is connected to the control gate line CGL<i> through a contact C4. A control gate CG of the transistor FGT12 is connected to the control gate line CGL<i+1> through a contact C4. Drain regions of the transistors FGT11, FGT12 are connected to a bit line BL through contacts C1. A select control gate SGC is connected to a word line WL<i,i+1> common to the two memory cells through a contact C3. Each floating-gate transistor FGT11, FGT12 also has a source terminal coupled to a source line SL through a respective select transistor ST11, ST12. The select transistors ST11, ST12 share a same select control gate SGC. The two memory cells C11, C12 are referred to as twins due to the fact that they share the same select control gate SGC and the same bit line BL. The channel regions CH1, CH2 of the transistors FGT11, FGT12, ST11, ST12 are at the electric potential of the well PW, as represented by dotted lines. Finally, the source regions of the transistors ST11, ST12 are electrically coupled to the source line SL. The latter can be connected through a contact C5 to a main source line produced in a layer of metal.
Each common control gate SGC is preferentially a vertical gate embedded in a substrate receiving the memory array, the source line SL also being an embedded line. The common control gates SGC, or twin memory cell select gates, are connected to the word line WL<i,i+1>.
Such memory cells are erased or programmed by the channel, i.e., by putting the substrate to a positive erase voltage or negative programming voltage causing electric charges to be extracted from their floating gates or electric charges to be injected into their floating gates, by Fowler-Nordheim effect.
More particularly, a memory cell is erased by combining the positive voltage applied to the substrate with a negative voltage applied to the control gate CG of its floating-gate transistor, while the control gate of the floating-gate transistor of the twin memory cell receives a positive erase-inhibit voltage preventing it from being simultaneously erased.
Similarly, a memory cell is programmed by combining a negative voltage applied to the bit line BL and to the substrate PW with a positive voltage applied to the control gate CG of its floating-gate transistor, while the control gate of the floating-gate transistor of the twin memory cell receives a negative program-inhibit voltage preventing it from being simultaneously programmed.
Finally, a memory cell is read by applying a positive voltage to the control gate of its floating-gate transistor, as well as a positive voltage to the corresponding bit line, while the twin memory cell, which is connected to the same bit line, receives on its control gate a negative read-inhibit voltage preventing it from being simultaneously read.
This memory array structure having twin memory cells comprising a shared vertical select gate embedded in the substrate, offers the advantage of having a small footprint.
This conventional memory array and memory cell structure also includes a word line decoder capable of applying a positive read voltage to a memory cell to be read, while applying a negative read-inhibit voltage to its twin memory cell, as explained above.
It could thus be desirable to simplify the line decoder. It could also be desirable to optimize the operations of reading and programming the memory cells, in particular in terms of current consumption.